SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
INT Output
Port P1 can be configured as a latching interrupt out-
put, INT , that flags any transients on any combination of
selected ports configured as inputs. Configurable logic
gate outputs can also be monitored as readback inputs
with the same options as normal I/O port inputs. Any
transitions occurring at the selected inputs assert INT
low to alert the host processor of data changes at the
selected inputs. Reset INT by reading any ports I/O
registers (0x01 to 0x09).
Standby Mode
Upon power-up, the MAX7302 enters standby mode
when the serial interface is idle. If any of the PWM
intensity control, blink, or debounce features are used,
the operating current rises because the internal PWM
oscillator is running and toggling counters. When using
OSCIN to override the internal oscillator, the operating
current varies according to the frequency at OSCIN.
When the serial interface is active, the operating cur-
rent also increases because the MAX7302, like all I 2 C
slaves, has to monitor every transmission. The bus
timeout and debounce circuits use the internal oscilla-
tor even if OSCIN is selected.
Internal Oscillator and OSCIN/OSCOUT
External Clock Options
The MAX7302 contains an internal 32kHz oscillator. The
MAX7302 always uses the internal oscillator for bus
timeout and for debounce timing (when enabled). It is
used by default to generate PWM and blink timing. The
internal oscillator only runs when the clock output
OSCOUT is needed to keep the operating current as
low as possible.
The MAX7302 can use an external clock source instead
of the internal oscillator for the PWM and blink timing.
The external clock can range from DC to 1MHz, and it
connects to the P2/OSCIN port. The P3/OSCOUT port
provides a buffered and level-shifted output of the inter-
nal oscillator or external clock to drive other devices.
Select the P2/OSCIN and P3/OSCOUT port options
using the device configuration register 0x67 bits D2
and D3 (see Table 4).
The P2/OSCIN port is overvoltage protected to supply
voltage V LA , so the external clock can exceed V DD if
V LA is greater than V DD . The port P2 register (see
Tables 2 and 6) sets the P2/OSCIN logic threshold
(30%/70%) to either the V DD supply or the V LA .
Use OSCOUT or an external clock source to cascade
up to four MAX7302s per master for applications requir-
ing additional ports. To synchronize the blink action
across multiple MAX7302s (see Figures 4 and 5), use
OSCOUT from one MAX7302 to drive OSCIN of the
other MAX7302s. This process ensures the same blink
frequency of all the devices, but also make sure to syn-
chronize the blink phase. The blink timing of multiple
MAX7302s is synchronous at the instant of power-up
because the blink and PWM counters clear by each
MAX7302’s internal reset circuit, and by default the
MAX7302s’ internal oscillators are off upon power-up.
Ensure that the blink phase of all the devices remains
synchronized by programming the OSCIN and
OSCOUT functionality before programming any feature
that causes a MAX7302’s internal oscillator to operate
(blink, PWM, bus timeout, or key debounce). Configure
the RST input to reset the internal timing counters used
for PWM and blink by setting bit D1 of device configu-
ration register 0x26 (see Table 3).
PWM and Blink Timing
The MAX7302 divides the 32kHz nominal internal oscilla-
tor OSC or external clock source OSCIN frequency by 32
to provide a nominal 1kHz PWM frequency. Use the reset
MAX7302
P3/OSCOUT
MAX7302
P2/OSCIN
MAX7302
MAX7302
P2/OSCIN
MAX7302
MAX7302
P3/OSCOUT
P2/OSCIN
P3/OSCOUT
P2/OSCIN
Figure 4. Synchronizing Multiple MAX7302s (Internal Oscillator)
14
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